The present invention relates to a semiconductor integrated circuit device and manufacturing technology related thereto; and, more particularly, the invention relates to a technology for reducing variations in threshold voltage of a scaled-down MISFET (Metal Insulator Semiconductor Field Effect Transistor).
Element isolation trenches formed by embedding an insulating film, such as a silicon oxide film, into grooves or trenches defined in a semiconductor substrate have excellent advantages as compared with a field insulating film formed by a conventional selective oxidation (Local Oxidation of Silicon; LOCOS) method. Such element isolation trenches are advantageous even over the ensuring of sub-threshold characteristics, and reductions in junction leaks and backgate effects, in that (a) element isolation intervals can be reduced, (b) control of element isolation film-thickness is easy and a field reversal voltage is easy to set, and (c) an impurity is implanted in the side walls and bottom in each trench in parts to thereby allow separation of an inversion-preventing layer from a diffused layer and a channel region for each element.
In order to define element isolation trenches in a semiconductor substrate (hereinafter referred to simply as a xe2x80x9csubstratexe2x80x9d), for example, the substrate is first etched with a silicon nitride film as a mask to thereby define grooves or trenches in the substrate in an element isolation region. Subsequently, a method is employed of depositing a silicon oxide film on the substrate so as to embed the silicon oxide inside the trenches, and, thereafter, the unnecessary silicon oxide film lying outside each trench is removed by chemical mechanical polishing (CMP). This type of technology has been described in, for example, 1997 Symposium on VLSI Tech. Digest of Tech. Papers pp. 121-122.
However, a problem has been pointed out in that a phenomenon (called xe2x80x9ckink characteristic or hump characteristicxe2x80x9d, for example) occurs, such that, when a gate electrode of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) is formed on (i.e., insulatedly on) the substrate with the element isolation trenches defined therein by using the above-described method, the threshold voltage (Vth) is locally reduced at an end of an active region brought into contact with each element isolation trench, and a channel is inverted at a low gate voltage (Vg) to thereby allow a drain current to flow.
The reduction in threshold voltage is considered to result from the fact that, for example, some of an impurity for threshold voltage control, which has been introduced into the substrate in the active region, is diffused into the silicon oxide film in each element isolation trench by in-manufacturing process heat treatment to thereby reduce the concentration of the impurity at each end of the active region, and the thickness of a gate insulator formed at each end of the active region becomes thin due to a reduction (recess) in the thickness of the silicon oxide film at the end of each element isolation trench, which occurs during the manufacturing process, whereby a high electric field concentrates on the thickness-reduced gate insulator.
Japanese Patent Application Laid-Open No. Hei 8-55985, showing Japanese Patent Application Publication corresponding to U.S. Pat. No. 5,567,553, discloses a technology in which, as a countermeasure against the problem that a leakage current increases in a cut-off region due to a reduction in threshold voltage, which is developed at an end of an active region, the gate length (channel length) of a gate electrode in a region, which crosses the boundary between the active region and each element isolation trench, is set longer than the gate length thereof in a central portion of the active region, whereby the threshold voltage at the end of the active region is set to substantially the same value as the threshold voltage in the central portion of the active region.
The article entitled xe2x80x9cAnomalous Gate Length Dependence of Threshold Voltage of Trench-Isolated Metal Oxide Semiconductor Field Effect Transistorxe2x80x9d (T. Oishi, K. Shiozawa, A. Furukawa, Y. Abe and Y. Tokuda, JJAP 37(1998) L852-L854) has discussed the influence of the concentration of an electric field on an end of an active region upon gate length dependence of a threshold voltage, using a gate electrode (I type gate) having a linear pattern and a gate electrode (H type gate) in which branch patterns extending in a direction orthogonal to the linear pattern are provided at both ends of the linear pattern and in which the linear pattern does not cross the boundary between the active region and each element isolation trench.
The present inventors have a low power consumption type SRAM (Static Random Access Memory) used as a data memory for a portable electronic device or the like in the works. In the present SRAM, a reference voltage generating circuit for generating a reference voltage (Vdd) from an external source voltage (Vcc) is provided as a part of the peripheral circuits. The reference voltage generating circuit is a circuit which comprises a plurality of enhancement type MISFETs and a plurality of depletion type MISFETs and which generates a reference voltage (Vdd) according to the difference between a threshold voltage of each enhancement type MISFET and a threshold voltage of each depletion type MISFET. Further, the MISFETs, which constitute the reference voltage generating circuit, are to be operated at a very small current, such as about 10 nA, to promote low power consumption as opposed to the case where MISFETs constituting another peripheral circuit, such as an input/output circuit, are operated at a current of about a few xcexcA.
The fabrication of each MISFET to be operated at a small current needs to have the impurity concentration of the substrate increased in a region in which a channel for the MISFET is formed, as compared with that of the substrate in a region in which another MISFET is formed, thereby increasing the threshold voltage thereof. However, when the impurity concentration of the substrate in the channel-formed region is set high, the amount of diffusion of the impurity into the silicon oxide film at the end of the active region also increases, and the difference between the impurity concentration at the end of the active region and that in a central portion thereof becomes large. Therefore, a kink will be easily created due to the reduction in threshold voltage at the end of the active region in cooperation with a variation in the amount of a recess at an end of each element isolation trench, which is developed in a manufacturing process.
Since the MISFETs, which constitute the reference voltage generating circuit, are designed so as to operate with a small current, such a small kink as to offer no problem in another circuit operated at a relatively large current can also result in the occurrence of a circuit""s malfunction. Particularly, since the reference voltage generating circuit adopts a circuit system wherein the reference voltage is generated according to a difference between the threshold voltage of each enhancement type MISFET and that of each depletion type MISFET, the reference voltage also varies when the threshold voltage of each MISFET varies due to the occurrence of the kink, whereby a desired reference voltage cannot be obtained. The reference voltage generating circuit brings about a problem in that, since an operating current therefor and a kink-based leakage current are substantially identical to each other in level, the reference voltage varies due to the occurrence of the kink.
An object of the present invention is to provide a technology capable of reducing a variation in threshold voltage of each scaled-down MISFET.
Another object of the present invention is to provide a technology capable of preventing a malfunction of a circuit comprised of MISFETs each operated at a small current.
The above, other objects and novel features of the present invention will become apparent from the description provided in the present specification and from the accompanying drawings.
A summary of typical aspects of the invention disclosed in the present application will be explained in brief as follows:
(1) There is provided a semiconductor integrated circuit device according to the present invention, comprising a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench, and wherein a first gate electrode of the first MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on (i.e., insulatedly on) the substrate in the first active region, the gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than the gate length thereof in a central portion of the first active region , and the first gate electrode in the boundary region covers the whole or entirety of one side extending along a gate-length direction, of the boundary region and parts of two sides thereof extending along a gate-width direction.
(2) There is provided a semiconductor integrated circuit device according to the present invention, comprising a first MISFET formed on a substrate in a first active region whose periphery is defined by an element isolation trench, and a second MISFET formed on the substrate in a second active region whose periphery is defined by the element isolation trench, and wherein a first gate electrode of the first MISFET, which crosses the first active region so as to extend from one end thereof to the other end thereof, is formed on (i.e., insulatedly on) the substrate in the first active region, a second gate electrode of the second MISFET, which crosses the second active region so as to extend from one end thereof to the other end thereof, is formed on (i.e., insulatedly on) the substrate in the second active region, the gate length of the first gate electrode in a boundary region defined between the first active region and the element isolation trench is greater than a gate length thereof in a central portion of the first active region, and the gate length of the second gate electrode in a boundary region defined between the second active region and the element isolation trench is substantially equal to a gate length thereof in a central portion of the second active region.